The present invention relates to a package structure incorporating a semiconductor device.
In recent years, high-density high integration semiconductor integrated circuits have been developed. Correspondingly, an LSI chip to be used has been remarkably large-scaled. Also, its heat density has been increasingly enhanced. To deal, with such a situation, there has been widely used a pin-grid-array package in which a great number of terminals for outer connection are arranged in a matrix shape on one surface of a package substrate.
A general structure of the pin-grid-array package is roughly classified in two types, i.e. "cavity-up" type and "cavity-down" type in view of manner of incorporating a chip. The cavity-up type is a structure as shown in FIG. 2 in which a chip carrier incorporating the chip looks up. The cavity-down type is a structure as shown in FIG. 3 in which a chip carrier incorporating the chip looks down.
Referring to FIG. 2, the structure of the cavity-up type package will be explained below. A chip 1 is fixedly attached to an insulating base substrate 6 through a fixing layer 3. Electric connection is made from the chip 1 to electrode part (not shown) on the insulating base substrate 6 through e.g. wire bondings 2, and further to pin-like terminals 5 for outer connection through conductive layers 4 in the insulating base substrate 6. Although in FIG. 2, wirings are extended in the substrate using a multi-layer plate as the insulating base substrate, they may also be extended by means of thin films and the like provided on the insulating base substrate 6 so as to be connected with the outer connection terminals 5 through conductive parts vertically provided within the insulating base substrate 6. Airtightness of the package is important from the viewpoint of reliability in the correct operation of the LSI chip, etc. In order to assure the airtightness of the package, the insulating base substrate 6 on which the chip is mounted is sealed by an insulating cap substrate 8 using e.g. soldering so as to shut out the outer environment. In the package having such a structure as mentioned above, heat generated in the chip 1 propagates to the insulating base substrate 6 through the chip fixing layer 3. The package is inserted and fixed onto a printed board through the outer connection terminal pins 5. In this case, the distance between the base substrate 6 and the printed board is as short as several millimeters. Thus, compulsory cooling from below the base substrate provides only slight effect. Accordingly, heat spreads in the insulating base substrate 6 and propagates to the insulating cap substrate 8 via a package sealing layer 7. And the heat propagates to a fin 9 fixed to the insulating base substrate 6 and is radiated therefrom.
Explanation will be given for the structure of the cavity-down type package of FIG. 3. The chip 1 is fixedly attached to the insulating base substrate 6. Electric connection is made from the chip 1 to electric part (not shown) on the insulating cap substrate 8 through e.g. wire bondings 2, and further to the pin-like terminals 5 for outer connection through the conductive layers 4 in the insulating cap substrate 6. In order to assure the airtightness of the package, the insulating cap substrate 8 incorporating the conductive layers 4 is sealed by a sealing cap 12 using e.g. soldering. In the package having such a structure, heat generated in the chip 1 propagates to the insulating base substrate 6 through chip fixing layer 3. And the heat spreads in the insulating base substrate 6 and propagates to the fin 9 fixed thereto thereby to be radiated therefrom.
In recent years, there has been proposed a structure in which a multi-layer is not used in the insulating cap substrate to extend the wirings, as disclosed in JP-A-62-106635. In this structure, the wirings are extended on the insulating base substrate on which the chip is mounted and outer connection terminal pins are provided on the ends of the wirings. An insulating cap substrate having a large number of through-holes is also prepared. The outer connection terminal pins on the insulating base substrate are fit into the through-holes of the insulating cap substrate. And the insulating base substrate is sealed in its periphery and also the through-holes through which the outer connection terminal pins are passed are sealed with soldering, resin, etc.
Further, there is proposed in JP-A-62-9649 a structure in which a wiring layer is formed in the substrate on which a semiconductor chip is mounted and a cap for sealing the semiconductor chip traverses the wiring layer. In this structure, the wiring layer is partially sealed by the cap but not entirely covered with the cap so that it must be covered with other means.
The semiconductor device package structures as mentioned above have the following problems to be solved.
The cavity-up type structure has a defect of a long heat propagation path. Heat generated in the chip must pass the long heat propagation path consisting of the chip fixing layer 3, the insulating base substrate 6, the package sealing layer 7, the insulating cap substrate 8 and the fin 9. Thus, the cavity-up type package structure is poor in its cooling efficiency and large in its heat resistance. This make it difficult to incorporate, in the package structure, a chip which has been very highly densified or integrated in recent years to have a high heat generation density.
On the other hand, in the cavity-down type package structure as shown in FIG. 3, heat generated in the chip is radiated via the chip fixing layer 3, the insulating base substrate 6 and the fin 9. Thus, the heat propagation path consisting of the sealing layer and the cap is omitted so that the heat propagation path in the cavity-down structure is shorter than that in the cavity-up structure. Therefore, the cavity-down structure is more advantageous than the cavity-up structure with respect to their cooling efficiency.
However, the cavity-down package structure also has the following disadvantages.
First, the cavity-down structure becomes complicated in its structure. Since the chip looks down, the electric connection from the chip to the outer connection terminal pins 5 is more complicated than the cavity-up structure. Also, since the chip and the outer connection terminals are located on the same side, it is difficult to make the wire bonding, which requires some particular contrivance in assembling the package. Further, since in view of the structure, the wire bonding is made directly from the chip onto the cap substrate, in order to extend the wiring, the cap substrate must be constructed in a multi-layer structure. Moreover, since the outer connection terminal pins 5 can not be provided on the cap 12 for holding the airtightness of the package, the area where the outer connection terminal pins can be arranged is smaller than the cavity-down package structure.
Secondly, the cavity-down structure provides reduced transmission speed due to its complicated structure. The transmission speed is reduced as the permittivity is increased. Thus, the conventional cavity-down structure, where transmissions travels a relatively long path of ceramic that has a larger permittivity than plastic, is inferior to the cavity-up structure in its transmission characteristic. Therefore, the conventional cavity-down structure can not sufficiently satisfy the increasing demand for high speed transmission experienced in recent years.
The cavity-down structure proposed in the above JP-A-62-106635, which seemed to provide a transmission speed substantially equal to the cavity-up structure, has the disadvantages of complicated steps of passing the outer connection terminal pins through the through-holes and thereafter sealing the through-holes. Further, the structure proposed in the above JP-A-62-9649 has a problem that the wiring layer is not entirely covered with the cap.